THE VLSI ARCHITECTURE OF THE THREE OPEREND BINARY ADDER HAS A HIGH-SPEED AND AREA-EFFICIENT DESIGN

Abstract

Addition in mathematics is a fundamental ability. When it comes to designing specific DSP applications and microprocessors, VLSI technology is frequently utilised. The ability to add two binary integers is another benefit, as is the role it plays in a wide range of mathematical operations. If you utilise an additive to produce three operator-carrying adders, this project will allow you to generate three operand adderSums. Thereby, a more energy-efficient and faster localised construction is given, which makes use of number-based prediction to produce a highly compact triple binary adder (log2 n).