Abstract

With the rapid proliferation of the internet and digital media, the transmission and reproduction of digital content have become incredibly convenient. However, this convenience comes with the drawback of digital piracy and unauthorized distribution, as digital products can be easily duplicated without loss in fidelity. Protecting the intellectual property rights of digital media is crucial in this digital era. Digital watermarking emerges as a powerful technique for content authentication, illegal duplication detection, and securing intellectual property. Digital watermarking can be employed to prevent unauthorized use, claim ownership, and even hide secret messages within digital media. Watermarking algorithms embed the watermark within the digital object, while verification algorithms ascertain the presence of the watermark and its associated data bits. In VLSI implementation of digital watermarking systems, it is imperative to optimize for low area usage, minimal delays (both path and logical), and efficient resource utilization. This research focuses on the development of a hybrid stationary wavelet transform-based watermarking system, aiming to address the challenges of conventional wavelet transform-based VLSI systems, particularly those related to down-sampling. By leveraging VLSI fundamentals, this work strives to achieve a more efficient and robust digital watermarking solution.

Description