Abstract

Design selection plays a vital role in selecting the most suitable adder for a particular application based on the requirements of delay and area. Particularly, with the advent of domain specific architectures, customized arithmetic operations are prevalent. Tailoring these adders for the specific application can enhance the performance and the efficiency of the specific architecture. These adders are essential for algorithmic customization. This paper discusses various techniques of carry select adders, Brent Kung adders. The gate count of 32-bit adders is calculated manually and the delay has been analyzed using Xilinx Vivado.

Description

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